Self-aligned silicone process for low resistivity contacts to thin film silicon-on-insulator mosfets

ABSTRACT

A silicide processing method for a thin film SOI device including depositing a metal or an alloy on a gate and a source/drain structure formed in a silicon-on-insulator film, reacting the metal or alloy at a first temperature with the silicon-on-insulator film to form a first alloy, etching the unreacted layer of the metal (or alloy) selectively, depositing a Si film on the first alloy, reacting the Si film at a second temperature to form a second alloy, and etching the unreacted layer of the Si film selectively.

U.S. GOVERNMENT RIGHTS IN THE INVENTION

[0001] The subject matter of the present Application was at leastpartially funded under the Grant No. N66001-97-1-8908 from the U.S.Defense Advanced Research Projects Agency (DARPA).

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention generally relates to silicon-on-insulator(SOI) MOSFETs and specifically, a self-aligned silicide (salicide)process for thin film SOI MOSFETs having low resistivity contacts.

[0004] 2. Description of the Related Art

[0005] Conventionally, a reduction of a short channel effect in asilicon-on-insulator (SOI) MOSFET has been addressed by using ultra-thinsilicon films (e.g., having a thickness substantially within a range ofabout 50 nm to about 3 nm). However, using an ultra-thin SOI film canresult in high source/drain series resistance. A portion of the highsource/drain series resistance can be reduced by using a self-alignedsilicide (salicide) contact (e.g., for a discussion of salicides, seeLisa T. Su et al., “Optimization of the series resistance in sub—0.2 μmSOI MOSFET's”, Electron Device Letters, 15(9), p. 363, September 1994).

[0006] The conventional salicide process has been limited to bulk orthick SOI films (e.g., for purposes of the invention, a “bulk” or“thick” SOI film is thicker than 100 nm). Reduction of a SOI filmthickness to an estimated 10 nm precludes the use of conventionalsalicide. That is, if the amount of silicon consumed by the formation ofthe silicide alloy becomes a large portion of the initial SOI filmthickness, then the contact area will decrease, leading to an increasein the contact resistance. Further, even if a conventional salicide wasused with thin films, there is no guarantee of low parasitic resistancebecause an ultra-thin silicon film may be completely consumed during thesilicide formation. Further, the conventional salicide process can forma metal-rich silicide which is characterized by higher resistance.

[0007] In the case of a thin SOI film, the percentage of the SOIconsumed by the silicide considerably affects the series resistance. Ithas been demonstrated that when 80% or more of the SOI layer isconsumed, the series resistance begins to increase as a result of areduction in the contact area (e.g., see Su et al., supra).

[0008] Alternatively, if the silicide layer is made extremely thin(e.g., less than 30 nm) to avoid consuming the thin SOI film, then thesilicide layer loses its efficiency in reducing the series resistance.For example, if the silicide is in the thick regime, then a reduction ofthe silicide thickness would roughly yield a proportional increase inthe series resistance. This linear behavior would hold down to about 20nm (depending on the silicide metal). A thinner silicide film mayexhibit nucleation problems and some of the phases may not form. All ofthis would lead to a very steep increase in the contact resistance.

[0009] The series parasitic resistance must be minimized in order tofacilitate the fabrication of high performance thin film SOI MOSFETs.The conventional salicide process is not applicable to the production ofultra-thin SOI MOSFETs, and therefore a new salicide process is requiredto overcome the problems of the conventional method.

[0010] Further, the conventional method and structures are deficient intheir silicide/SOI interface roughness.

SUMMARY OF THE INVENTION

[0011] In view of the foregoing and other problems of the conventionalmethods and structures, an object of the present invention is to providea new salicide process applicable to the production of ultra-thin SOIMOSFETs (e.g., having a thickness substantially within a range of about3 nm to about 100 nm).

[0012] It is a further object to provide a new salicide process in whichless of the thin SOI film is consumed, produces a thicker SOI film in asource/drain region, and is a self-aligned process.

[0013] Additionally, a further object of the invention is to stay withinthe thermal budget allowed for the production of conventional MOSFETsusing the conventional salicide process. The thermal budget consists ofboth the temperature and the time length at which the wafer was held ata given temperature. Typically, to minimize the thermal budget the waferis annealed by rapid thermal annealing (RTA) to form the silicide alloy.For example, to form the CoSi₂ phase from the CoSi phase the wafer isannealed at about 750° C. for 60 seconds.

[0014] In a first aspect of the invention, a method for fabricating asemiconductor device, includes depositing a buried oxide layer on asubstrate, applying a silicon layer to the buried oxide layer, forming asource and drain in the silicon layer, forming a gate on the layer ofsilicon, and depositing a metal on the gate and the source and drain, toform the silicide for the semiconductor device.

[0015] In a second aspect of the present invention, a silicideprocessing method for a thin film silicon-on-insulator (SOI) device,includes depositing a metal on a gate and a source and drain formed in asilicon-on-insulator (SOI) film, reacting the metal at a firsttemperature with the SOI film to form a first alloy, selectively etchingthe unreacted layer of the metal, depositing a Si film on the firstalloy, reacting the Si film at a second temperature to form a secondalloy, and selectively etching the unreacted layer of the Si film.

[0016] In the method of the present invention, preferably a thin-film ofcobalt (Co) is deposited on a substrate and is reacted with silicon (Si)at a low temperature to form an alloy of Co₂Si (e.g., having ametal-rich phase). The Co which is not reacted is removed by selectiveetching.

[0017] This step is similar to the etching step in the conventionalsalicide processing, but in the conventional process, a highertemperature anneal is used so the etching is usually performed at theCoSi formation stage. After the etching step, a non-crystalline film ofSi or poly-Si is deposited and subsequently annealed to form the alloy(CoSi₂) followed by selective etching of the un-reacted silicon.

[0018] In this manner, a reaction of Co to initially form Co₂Si,minimizes the silicon consumption of the thin SOI film. The consumptionof the thin SOI film is additionally reduced by the deposition of asilicon or poly-silicon film on the Co₂Si.

[0019] The present invention extends the use of a salicide-like processto thin SOI films, which are expected to be used in future SOI MOSFETs.Such thin-film SOI films will be advantageous in making the devicessmaller, reducing the source/drain to substrate overlap capacitance, andeliminating the floating body voltage.

[0020] Further, the invention provides a superior solution to thealternative method(s) which include a raised source/drain by epitaxy.

BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The foregoing and other objects, aspects and advantages will bebetter understood from the following detailed description of a preferredembodiment of the invention with reference to the drawings, in which:

[0022] FIGS. 1-6 illustrate a self-aligned method for forming lowresistivity contacts to thin film SOI MOSFETs, and more specifically:

[0023]FIG. 1 shows a conventional MOSFET device to be silicided;

[0024]FIG. 2 shows a thin film of metal (e.g., Co) deposited on thedevice of FIG. 1;

[0025]FIG. 3 shows the formation of an alloy including the cobalt afterexposure to a low-temperature processing;

[0026]FIG. 4 shows an amorphous Si film deposition on the alloy;

[0027]FIG. 5 shows the device after an annealing step at hightemperature; and

[0028]FIG. 6 shows the device after un-reacted silicon has been removedby selective etching.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT OF THE INVENTION

[0029] Referring now to the drawings, and more particularly to FIGS.1-6, there is shown a preferred embodiment of the method of making of aself-aligned silicide which is applicable to the standard MOSFETstructure, and also to non-conventional MOSFETs and structures accordingto the present invention.

[0030] Referring now to FIG. 1, a conventional MOSFET structure 100 isshown having a substrate 1 formed of silicon, a buried oxide layer 2(e.g., silicon oxide layer), an SOI layer 3 which thickness noted byt_(si), a gate dielectric 6A (e.g., SiO₂), sidewall spacers 6B formed ofnitride or oxide, a gate 7 (e.g. doped poly-Si, or metal), and a source4 and a drain 5 maid into the SOI film 3, typically by an implant.

[0031] The inventive method is directed to making a self-alignedsilicide which is applicable to the standard MOSFET structure, and alsoto non-conventional MOSFETs and structures. For ease of discussion, thepresent invention will be applied to the conventional MOSFET of FIG. 1.

[0032] However, although the process flow is demonstrated using aconventional MOSFET structure, it is applicable to a wide variety ofstructures. Metals, other than Co, that are used for silicides (e.g.,Ti, Ni, Pd, Pt and alloys thereof) can be used with the presentinvention.

[0033] Referring to FIG. 2, a metal 20 (e.g., Co, Ni, Ti, Pd, Pt oralloys thereof) is deposited in a thickness within a range of about 7nm, and is reacted with silicon in the source 4, drain 5, and gate 7regions at a low temperature T₁. It is noted that if the temperature istoo low, no reaction will take place. On the other hand, if thetemperature is too high, then the silicide phase of CoSi will be formed.Since the temperature window over which the metal-rich phase Co₂Si isformed is narrow, it is difficult to achieve only this phase during thefirst anneal. To extend the temperature window, a mixture of 80% Co and20% Si may be deposited (e.g., by co-sputtering or evaporation from aSi_(0.2)Co_(0.8) target). The temperature window for the formation ofthe Co₂Si out of the Si_(0.2)Co_(0.8) mixture is about 337° C. to about487° C. The use of a 80% Si and 20% Co to extend the temperature windowis described in U.S. patent application Ser. No. ______, Cyril Carbalet. al, “Method for self-aligned formation of silicide contacts usingmetal silicon alloys for limited silicon consumption and for reductionof bridging”, filed on ______, having IBM Docket No. YOR900-0044,incorporated herein by reference.

[0034] As shown in FIG. 3, the alloy Co₂Si 30 is formed, as a result ofapplying the low temperature (e.g., T₁) in the anneal process to thestructure of FIG. 2. (The thickness depends on the initial Co filmthickness. One angstrom of Co yields 1.47 angstroms of Co₂Si. Thetypical Co film thickness is about 7 nm. Using the conversion ratiostated above, a 10.3 nm thick film of Co₂Si will be obtained after thefirst anneal.) An upper layer of the cobalt 20 (e.g., over the alloyCo₂Si 30) is unreacted Co 20.

[0035] That is, in the standard process, all of the Co which isdeposited over a Si surface will react with the silicon surface and willform a silicide. On the other hand, the Co that was deposited overdielectric surfaces such as the oxide or nitride sidewalls cannot reactwith the Si surface and will remain as unreacted Co. FIG. 3 demonstratesa case in which some Co is left unreacted on top of the silicide. Asdescribed above, this is not desirable in a manufacturing process. Yet,even if this does happen, the overall process of the invention will notbe affected except that the silicide film will be thinner than targeted.As such, the robustness of the process is clearly demonstrated. It isnoted that in most cases, there will be no unreacted Co.

[0036] For example, the unreacted cobalt 20 has a thickness dependent onthe anneal time/temperature, and is removed through selective etching.That is, a too short anneal may leave some of the Co unreacted. If thetemperature is too low, then the Co will not react with the SOI film.This step is similar to the etching step in the conventional salicideprocess with the exception that in the conventional salicide process theun-reacted Co is etched at the stage where CoSi is formed. It is notedthat the deposition of the a-Si may be carried out over the CoSi phase.However, by forming the CoSi phase, much more of the Si in the SOI layerwill be consumed. An example of a selective etching solution is 10:1H₂O₂:H₂SO₄ at 65° C.

[0037] Next, referring to FIG. 4, an amorphous Si (a-Si) or a poly-Sifilm 40 is deposited over the alloy Co₂Si 30. The a-Si film thicknessdepend on the initial Co film thickness. One unit of Co would require0.91 units of Si to form Co₂Si, 1.82 units of Si to form CoSi and 3.64units of Si to form CoSi₂. For example, suppose the process starts witha 7 nm Co film which are then reacted with the SOI film to form 10.3 nmfilm of Co₂Si. Assuming that all the Co will diffuse into the topdeposited a-Si, then it requires the a-Si film to be about 19 nm thick.A more realistic assumption is that more than half but not all the Cowill diffuse into the top film, so that a thinner film is actuallyneeded. The amorphous silicon or polysilicon film 40 is annealed at ahigh temperature T₂, (e.g., T₂>T₁). The temperature window for theformation of CoSi is about 481° C. to about 625° C. (at about 625° C.,CoSi₂ will start to form). Typical annealing temperature (T2) for thesecond anneal is about 750° C. These temperatures may vary slightlydepending on the doping species and concentration that were implantedinto the SOI film.

[0038] Hereinbelow, the amount of required Si in angstroms per angstromsof metal is described. Forming 1 angstrom of Co₂Si will take 0.91angstrom of Si, CoSi will take 1.82 angstroms of Si, and CoSi₂ will take3.64 angstrom of Si. If the a-Si layer is deposited on top of the Co₂Sifilm, then the Si consumption may be reduced by at least a half, sincethe Co₂Si film would be reacting on both top and bottom interfaces.

[0039] It is important to clean the top surface of the Co₂Si and removeany native oxide before the a-Si film deposition. The existence of suchan oxide at the interface may prevent the Co₂Si to react with thedeposited a-Si layer. The cleaning of the surface and the stripping of anative oxide may be achieved by Ar (argon) sputtering in the a-Sideposition chamber or by a short dip in a diluted HF acid.

[0040] As shown in FIG. 5, as a result of the annealing operation at ahigh temperature T₂, a layer of CoSi₂ 50 is formed under an unreactedlayer/portion 40A of the amorphous silicon or polysilicon film 40. Thethickness of the layer of un-reacted amorphous silicon/polysilicon layer40A depends on the initial thickness of the top a-Si layer 40. It isdesirable that all of the Co₂Si is transformed into CoSi₂, withoutconsuming the entire a-Si layer. The unreacted layer/portion 40A resultsfrom the supply of Si from the a-Si exceeding that which is needed toform CoSi₂. In other words, the a-Si layer was too thick.

[0041]FIG. 6 illustrates the selective etching of the layer ofun-reacted a-Si or poly-Si film 40 in a last phase.

[0042] Thus, with the invention, the reacting of the metal (e.g.,cobalt) in an annealing operation to initially form the alloy Co₂Si 30minimizes the silicon consumption of the SOI film 3.

[0043] Additionally, the deposit of the amorphous silicon or thepolysilicon film 40 on top of the alloy Co₂Si 30 further reducesconsumption of the SOI film 3 by a factor of two since at least half ofthe Co contained in the Co₂Si 30 will diffuse into the top amorphoussilicon/polysilicon film layer 40 at the high temperature anneal whichforms the CoSi₂.

[0044] The diffusivity of cobalt in polysilicon may be larger than insingle crystal (mono-crystal) silicon. Due to this diffusivitydifference between polysilicon and single crystal silicon, the hightemperature anneal will consume more of the top polysilicon layer thanthat of the bottom single crystal SOI film.

[0045] In an alternative embodiment, the invention can be modified sothat the first anneal is at an intermediate temperature, T₃ (e.g., T₃ isabout 550° C.), where CoSi is formed (T₁<T₃<T₂). The anneal process atthis temperature will consume more of the SOI film than a Co₂Siformation. However, it may provide a larger temperature window for theanneal.

[0046] The larger the temperature window, the easier it is to form agiven silicide phase without the risk of obtaining a mix phase. Thetemperature window for Co₂Si is about 20° C. wide if pure Co is used. Itmay be widened to about 100° C. by using Co_(0.8)Si_(0.2). The windowmay shift and vary depending on the SOI doping. This makes it difficultto obtain the Co₂Si phase if the window is narrow. If pure Co ratherthan Co_(0.8)Si_(0.2) is used, then it is easier to form CoSi due to itslarge temperature window of about 150° C.

[0047] Also, the etch selectivity of CoSi, with respect to Co, is higherthan that of Co₂Si with respect to Co. The advantages of thisselectivity include better reliability and precision of the resultingproduct. After the Co is reacted to form CoSi, the unreacted Co must beetched away. Otherwise, the source/drain regions will be shortened tothe gate. The etchant should be selective to CoSi. That is, it shouldonly remove the Co and leave the CoSi alloy intact. The etchingselectivity is typically higher if the alloy contains less Co and moreSi. Thus, CoSi is expected to be more resistant to the etch of Co thanCo₂Si. The remainder of the steps in the process are the same.

[0048] Thus, the present invention is optimized over the conventionaltechniques. That is, alternative conventional methodologies (e.g., whichare less desirable when contrasted to the embodiments of the inventiondescribed above), include thickening a SOI layer (by at least the amountthat will be consumed by the silicide in source and drain regions byusing selective epitaxial growth of silicon on these regions,fabricating different silicide thicknesses over gate, source and drainregions by laser melting, and the deposit of a silicon alloy(Co_(1-x)Si_(x), where x<0.2) to limit the amount of silicon consumed atsource, drain, and gates during silicide formation.

[0049] As mentioned above, the epitaxial growth of Si is performed bythickening a SOI layer in the source/drain regions through selectiveepitaxial growth of Si in these regions. This alternative has severaldisadvantages when compared to the process of the present invention.

[0050] First, the epitaxial growth has to be selective, otherwise Sigrowth will take place on the sidewalls of the device. This conditioncan lead to shorting the gate to the source and the drain. To avoid thisproblem, the choice of the sidewall material to use is narrowed becauseonly growth-resistant materials can be selected.

[0051] Further, the growth temperature is an important parameter indetermining the selectivity of the growth. The Si epitaxial growth losesselectivity at low growth temperatures. “Low growth temperatures” dependon the growth technique, and the sillicon source. The most selectivesource is SiCl₄, but it also requires the highest deposition temperature(about 900° C. to 1200° C.). Silane (SiH₄) can be used for lowtemperature deposition (as low as about 650° C.), but it exhibits verylittle selectivity, if any. Therefore, a sufficiently high growthtemperature (e.g., about 900° C.) is required to guarantee selectivity.The required high growth temperature may be in excess of the thermalbudget incurred in the conventional salicide process.

[0052] A further problem with producing a raised source/drain byepitaxial growth of silicon is the process robustness. Silicon epitaxyis very sensitive to surface preparation and cleaning. Different surfacetreatments can lead to different defects in the film. Oxide residuals(e.g., even an atomic monolayer) can prevent epitaxial growth.

[0053] Another problem with the epitaxial growth approach, known asgrowth rate dependency on feature size, can occur. In a chemical vapordeposition (CVD)-type epitaxy, the growth rate may be dependent on thetopography, the dimensions of the growth area, and the ratio between thegrowth to non-growth areas. This may lead to a growth of different filmthicknesses in devices that are embedded in different circuit layouts.This condition is an additional dimension that must be included in amanufacturing process, and hence require additional costs. The presentinvention does not require epitaxy, and is therefore not limited by thedifficulties imposed by epitaxy.

[0054] A second approach is siliciding by laser melting. This is arelatively new technique that allows the fabrication of differentsilicide thicknesses over the gate and over the source/drain region.This technique has not been applied in a manufacturing context andtherefore its usage in practice is unknown. The throughput of thetechnique may be lower than that achieved with the other techniques suchas raised source/drain, deposition of CoSi alloy, etc. Laser annealingis carried out per wafer, that is the wafers are processed sequentially,one at a time. Raised source/drain epitaxy and the present invention areparallel techniques in the sense that the entire wafer lot may beprocessed together (e.g., a single deposition is carried out on allwafers).

[0055] The invention uses conventional fabrication techniques, and doesnot have a throughput problem. The thermal budget required by theinvention is the same as in a conventional salicide process.

[0056] A third approach employs deposition of a Co_(1-x)Si_(x) alloy tolimit the source and drain silicon consumed during silicide formation.This approach is limited to a composition that has a sufficiently smallconcentration of Si (x<0.2) permitting the alloy deposited on the oxidesidewalls to be removed by selective etching.

[0057] It is noted that the invention can utilize this technique tofurther decrease the Si consumption by depositing Co_(1-x)Si_(x) insteadof pure Co as mentioned above. The second advantage of Co_(1-x)Si_(x) isthe larger temperature window which is available for the formation ofthe metal-rich phase.

[0058] Thus, the present invention overcomes the above-mentioned andother problems of the conventional techniques and allows forming asilicon-on-insulator (SOI) MOSFET having ultra-thin silicon films andwhile preventing (or at least minimizing) the high source/drain seriesresistance and maintaining its efficiency. Thus, bulk or thick SOI filmsare unnecessary with the inventive method. Further, series parasiticresistance is minimized in order to facilitate the fabrication of highperformance thin film SOI MOSFETs with the inventive method.

[0059] While the invention has been described in terms of preferredembodiments, those skilled in the art will recognize that the inventioncan be practiced with modification within the spirit and scope of theappended claims.

[0060] The method and structure of the present invention are not limitedto a specific silicide-forming metal. Further, the invention, is notlimited to one particular device as described above, but can also beused in devices with a non-planar source/drain region, such as apolysilicon sidewall source drain (e.g., see P. M. Solomon, H. -S. P.Wong, “Method for Making Single and Double Gate Field Effect Transistorswith Sidewall Source Drain Contacts”, U.S. Pat. No. 5,773,331, Jun. 30,1998, incorporated herein by reference; and T. Yoshimoto et al.,“Silicided Silicon-Sidewall Source and Drain Structure for HighPerformance 75-nm gate length pMOSFETs,” 1995 Symposium on VLSITechnology, digest p.11).

What is claimed is:
 1. A method for fabricating a silicide for asemiconductor device, said method comprising: depositing a buried oxidelayer on a substrate; applying a silicon layer to said buried oxidelayer; forming a source and drain in said silicon layer; forming a gateon said layer of silicon; and depositing a metal or an alloy on saidgate and said source and drain, to form said silicide for saidsemiconductor device.
 2. The method, as claimed in claim 1, furthercomprising: reacting said metal or said alloy with said silicon to forma first alloy at said gate and said source/drain structure.
 3. Themethod, as claimed in claim 1, wherein said semiconductor devicecomprises a metal oxide semiconductor field-effect transistor (MOSFET)device.
 4. The method, as claimed in claim 1, wherein said metal isselected from one of a group consisting of cobalt, titanium, nickel,platinum, Pt_(x) Si_(1-x) alloy, palladium, Pd_(x) Si_(1-x) alloy, andCo_(x) Si_(1-x) alloy.
 5. The method, as claimed in claim 2, whereinsaid reacting is performed at a first temperature.
 6. The method, asclaimed in claim 2, wherein said reacting is performed within a range ofa first predetermined lower temperature to a second predetermined highertemperature.
 7. The method, as claimed in claim 6, wherein said reactingis performed at a third temperature, said third temperature beingintermediate said first and second temperatures.
 8. The method, asclaimed in claim 2, wherein said first alloy is an alloy selected fromthe group consisting of Co₂ Si and Co Si.
 9. The method, as claimed inclaim 2, wherein said first alloy is formed under an unreacted layer ofsaid metal or said alloy.
 10. The method, as claimed in claim 9, furthercomprising: etching said unreacted layer of said metal or said alloyselectively; depositing a Si film on said first alloy; and reacting saidSi film to form a second alloy.
 11. The method, as claimed in claim 10,wherein said film is a film selected from the group consisting of asingle crystal Si film and a polysilicon film.
 12. The method, asclaimed in claim 10, wherein said reacting said Si film is performed ata second temperature.
 13. The method, as claimed in claim 10, whereinsaid second alloy is formed under an unreacted layer of said Si film.14. The method, as claimed in claim 13, wherein said second alloy isCoSi₂.
 15. The method, as claimed in claim 13, further comprising:etching said unreacted layer of said Si film selectively.
 16. A silicideprocessing method for a thin film silicon-on-insulator (SOI) device,said method comprising: depositing a metal or an alloy on a gate and asource and drain formed in a silicon-on-insulator (SOI) film; reactingsaid metal or said alloy at a first temperature with said SOI film toform a first alloy; selectively etching said unreacted layer of saidmetal or said alloy; depositing a Si film on said first alloy; andreacting said Si film at a second temperature to form a second alloy.17. The method, as claimed in claim 16, wherein said reacting of said Sifilm at said second temperature reduces consumption of saidsilicon-on-insulator film by at least a factor of two.
 18. The method,as claimed in claim 16, further comprising selectively etching saidunreacted layer of said metal or said alloy.
 19. The method, as claimedin claim 16, wherein said second temperature is greater than said firsttemperature.
 20. The method as claimed in claim 16, further comprisingselectively etching said unreacted layer of said Si film.
 21. Themethod, as claimed in claim 16, wherein said metal is selected from oneof a group consisting of cobalt, titanium, nickel, platinum, Pt_(x)Si_(1-x) alloy, palladium, Pd_(x) Si_(1-x) alloy, and Co_(x) Si_(1-x)alloy.
 22. The method, as claimed in claim 16, wherein said reacting isperformed within a range of a first predetermined lower temperature to asecond predetermined higher temperature.
 23. The method, as claimed inclaim 16, wherein said first alloy is an alloy selected from the groupconsisting of Co₂Si and CoSi.
 24. The method, as claimed in claim 16,wherein said film is a film selected from the group consisting of asingle crystal Si film and a polysilicon film.
 25. The method, asclaimed in claim 16, wherein said second alloy is CoSi₂.